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PRELIMINARY DATA SHEET
MICRONAS
DPL 4519G Sound Processor for Digital and Analog Surround Systems
Edition Oct. 31, 2000 6251-512-1PD
MICRONAS
DPL 4519G
Contents Page 4 5 6 7 7 8 8 8 8 8 8 8 8 9 9 9 10 11 11 11 11 11 11 11 11 12 12 12 12 12 12 13 13 14 14 14 14 15 15 16 16 16 16 16 16 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2. 2.6.1.3. 2.6.1.4. 2.6.2. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.3.3. 2.6.3.4. 2.6.4. 2.7. 2.7.1. 2.7.2. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.9. 2.10. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. 3.1.5.1. 3.1.5.2. 3.1.5.3. 3.1.5.4. 3.2. Title Introduction Features of the DPL 4519G Application Fields of the DPL 4519G Functional Description Architecture of the DPL 4519G Family Preprocessing I2S Input Signals Selection of Internal Processed Surround Signals Source Selection and Output Channel Matrix Audio Baseband Processing Main and Aux Outputs Surround Processing Surround Processing Mode Decoder Matrix Surround Reproduction Center Modes Useful Combinations of Surround Processing Modes Examples Application Tips for using 3D-PANORAMA Sweet Spot Clipping Loudspeaker Requirements Cabinet Requirements Input and Output Levels for Dolby Surround Pro Logic SCART Signal Routing SCART Out Select Stand-by Mode I2S Bus Interfaces Synchronous I2S-Interface(s) Asynchronous I2S-Interface Multichannel I2S-Output Asynchronous Multichannel I2S-Input Digital Control I/O Pins Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Device and Subaddresses Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General DPL 4519G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C Controlling
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
DPL 4519G
Contents, continued Page 16 16 19 19 21 21 33 34 34 34 35 35 37 40 43 45 47 47 48 48 48 49 50 50 51 52 53 54 56 58 58 61 61 62 64 Section 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.4. 3.5. 3.5.1. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 5. 5.1. 5.2. 6. Title DPL 4519G Programming Interface User Registers Overview Description of User Registers Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes Micronas Dolby Digital chipset (with MAS 3528E) Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions (TA = 0 to 70 C) General Recommended Operating Conditions Analog Input and Output Recommendations Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Power Supply Rejection Analog Performance Appendix A: Application Information Phase Relationship of Analog Outputs Application Circuit Data Sheet History
License Notice: "Dolby Pro Logic" and "Dolby Digital" are trademarks of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
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Sound Processor for Digital and Analog Surround Systems The hardware and software description in this document is valid for the DPL 4519G version A1 and following versions.
PRELIMINARY DATA SHEET
In an application together with the Dolby Digital decoder MAS 3528E, eight channels (left, right, surround left, surround right, center, subwoofer, Pro Logic encoded left, Pro Logic encoded right) are fed in and processed in the DPL 4519G. Similar to the multichannel I2S input interface, the DPL is provided with an 8-channel I2S output interface, which can be connected to a MSP 44x0G. Therefore all 8 channels can be routed to each output in both ICs. The baseband processing including e.g. balance, bass, treble, and loudness is performed at a fixed sample rate of 48 kHz. Fig. 1-1 shows a simplified functional block diagram of the DPL 4519G. The DPL 4519G is pin-compatible to members of the MSP 34xx family. This speeds up PCB development for customers using MSPs. The software interface of the DPL 4519G is also largely the same as for members of the MSP family. The ICs are produced in submicron CMOS technology and are available in PQFP80, PLQFP64 and in PSDIP64 packages.
1. Introduction The DPL 4519G processor is designed as part of the Micronas chip set for digital and analog Surround Systems i. e. Dolby Digital, MPEG 2 Audio, or Dolby ProLogic. The combination of MAS 3528E, DPL 4519G, and MSP 44x0G is a complete 5.1 channel Dolby Digital decoder and playback solution, while DPL 4519G and MSP 44x0G alone, represent a complete Dolby Surround Pro Logic system. The DPL 4519G receives its incoming data via highly flexible I2S interfaces. The three I2S input interfaces can be configured as three asynchronous I2S inputs or two synchronous and one asynchronous interface. In the latter case, the asynchronous interface allows reception of 2-8 channels with arbitrary sample rate ranging from 8 to 48 kHz. The synchronization is performed by means of an adaptive high-quality sample rate converter.
I2S1
I2S Prescale
Main Sound Processing
DAC
Main Subwoofer
I2S2
I2S
Source Select
I S3
2
I2S (2..8-channel)
AUX Sound Processing
DAC
AUX
I2S (8-channel) DAC SCART Output Select SCART1
SCART1 SCART2 SCART3 SCART4 MONO
ProLogic processing
SCART2
Fig. 1-1: Simplified block diagram of the DPL 4519G
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PRELIMINARY DATA SHEET
DPL 4519G
1.1. Features of the DPL 4519G - 8-channel asynchonous I2S input interface (multichannel mode) + 2 synchronous I2S input channels (e.g. for MSP and ADR) or 3 asynchronous two-channel I2S input interfaces - Main and AUX channel with balance, bass, treble, loudness, volume - 5-band graphic equalizer for Main channel - Dolby Surround Pro Logic Adaptive Matrix - Micronas Effect Matrix - Micronas "3D-Panorama" virtualizer compliant to "Virtual Dolby Surround" technology - Micronas Panorama sound mode (3D Surround sound via two loudspeakers) - Noise Generator - Spatial Effect for Surround - 30-ms Surround delay - Surround matrix control: Adaptive/Passive/Effect - Center mode control: Normal/Phantom/Wide/Off - Surround reproduction control: Rear speaker, Front speaker, Panorama, 3D-Panorama - Two digital input/output pins controlled by I2C bus Fig. 1-2 shows a typical Dolby Digital application using DPL 4519G, MSP 4450G, and MAS 3528E.
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1.2. Application Fields of the DPL 4519G
PRELIMINARY DATA SHEET
S/PDI1 AC-3, MPEG L2, PCM or other Format PCM S/PDI2 Input Buffer Deemphasis
S/PDIF In 1/2
S/PDIF Out
PCM-Format (Lt/Rt or L/R or Lo/Ro) or Loop-through (e.g. DTS) Post Processing Delay Lines
L R Ls Rs C/ Sub Lt Rt
SPDO
2
MPEG
SID* SII* SIC*
AC-3
SOD3 SOD2 SOD1 SOD SOI SOC
Multipl.
I2S-In: Slave
SID SII SIC
Noise Gen.
Dolby Digital / Pro Logic Configurations Example 1: - internal L, C, R - internal woofer for low freq. of L, (C), R - ext. Surround speakers S L, SR - ext. Subwoofer for SUB channel.
18.432 MHz
Amp./ Osc.
PLL
Synth.
CLKO
MAS 3528E Dolby Digital Decoder MPEG-L2 Decoder
Example 2: - internal Left and Right used as C - internal woofer for low freq. of C - ext. L, R - ext. Surround speakers S L, SR - ext. Subwoofer for SUB channel.
Configuration Examples I2S-Mode:Multichannel Mode auf D0 (6 - 8 Channels, fs=32, 44.1 or 48 kHz, 16,18,....32 Bit) Main D/A analog Volume D/A analog Volume Aux ----SL SR SL SR ------Cint SUBext (Cint) Lext SUBext Rext normal Dolby Digital / Pro Logic 1 2
I2S_Inputs 1 I2S_WS3 I2S_CL3 2 3
I2S_1_L I2S_1_R I2S_2_L I2S_2_R
Bass Treble Balance Volume Bass Treble Balance Volume
AUDIO_ CL_OUT
2-8 Ch. Input (LT, RT,L, R SL, SR,C, SUB)
I2S_3_Lt I2S_3_Rt
18.432 MHz 6 Channel Loop-through or Dolby Pro Logic Decoder Dolby Digital Upgrade Module I2S_WS I2S_CL
SCART1 L R SL SR C SUB I2S_Out_L/R --Volume D/A ----Lt Rt L, R C, SUB SL, SR Lt, Rt Lt Rt L, R C, SUB SL, SR Lt, Rt
DPL 4519G
Pro Logic Decoder
Basic TVSound System I2S_WS3 I2S_CL3 I2S_WS I2S_CL
Dolby Digital: (L t, Rt, L, R, SL, SR, C, SUB) Pro Logic: (L t, Rt, L, R, C, SubW) I2S_Inputs 1 2 3 I2S_1_L I2S_1_R I2S_2_L I2S_2_R
I2S_3_Lt I2S_3_Rt I2S_3_L I2S_3_R I2S_3_SL I2S_3_SR I2S_3_C I2S_3_SUB
SoundProcess. Balance Volume Bass Treble Balance Volume Volume
D/A analog Volume
Main
L Subw R
Lint Subwint Rint
Cint Subwint Cint
18.432 MHz
D/A analog Volume
Aux L R SCART1 L R Lt Rt Lt Rt Lt Rt Lt Rt Lt Rt Lt Rt
2-8 Channel Serial Input
D/A SCART2
Volume
D/A
L R
SIF-IN SCART1_In
2 . . .
Demod
I2S_Out_L/R
L, R
L, R
L, R
A/D MSP 4450G
Multistandard Sound Processor
SCART4_In
Fig. 1-2: Typical DPL 4519G application
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(01hex)
Volume Balance DACM_R
Subwoofer Level Adjust
DACM_L D
Source Select
I2S_3 Resorting Matrix
C C 10 SUB SUB
(36hex ) (11hex ) (36hex)
Internal/External Switch
SC3_IN_L
SC3_IN_R SC2_OUT_L
SC4_IN_L
SC4_IN_R
MONO_IN SC2_OUT_R
DPL 4519G
Fig. 2-1: Signal flow block diagram of the DPL 4519G (input and output names correspond to pin names)
SCART Output Select
Micronas
Main Channel Matrix Bass/ Treble/ Loudness/ Equalizer
A DACM_SUB
(00hex)
I2S_DA_IN1 (sync. 48kHz)
Prescale
(16hex) (14hex) (2Chex)
I2 S Interface Beeper 6
Prescale
(12hex)
I2S1
5
(08hex) (02/03/04hex ) (20..25hex )
I2S_CL I2S_WS
I2S_DA_IN2 (sync. 48kHz) Volume Balanc A DACA_R
(31/32/33hex ) (30hex) (06hex)
I2 S Aux Channel Matrix
(09hex)
I2S2 Bass/ Treble/ Loudness
2. Functional Description
PRELIMINARY DATA SHEET
Interface
D
DACA_L
I2S_CL3 I2S_WS3
I2S_DA_IN3 (async. 8-48 kHz) 7 Rt
(0Bhex)
I2S Interface
synchronization
Lt I2S Interface
I2S Channel Matrix
I2S_DA_OUT (sync. 48kHz)
L
L 8 R
2.1. Architecture of the DPL 4519G Family
I2S3 R
Prescale
Fig. 2-1 shows a simplified block diagram of the IC.
SL SL 9 SR SR
Volume
D SCART1_L/R A
(07hex )
SCART1 Channel Matrix Noise Generator Surround Processing
(0Ahex)
(4Dhex) (49hex ) (4Ahex) (4Bhex) (4Chex)
Surround Channel Matrix
(48hex )
SC1_IN_L
SC1_OUT_L
SC1_IN_R
SC2_IN_L
SC2_IN_R
SC1_OUT_R
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DPL 4519G
2.2. Preprocessing I2S Input Signals The I2S inputs can be adjusted in level by means of the I2S prescale registers. The I2S_3 interface is able to receive more than two channels (see Section 2.6. on page 8). The incoming signals can be resorted by a programmable matrix in order to obtain a certain order, which means an unified postprocessing afterwards. Since the I2S_3 interface is asynchronous, incoming sound signals with arbitrary sample rates in the range of 8-48 kHz are interpolated to 48 kHz by means of an adaptive high quality sample rate converter. Therefore all subsequent processing is calculated on a fixed sampling rate, which even can be synchronized to I2S_WS e.g. to a MSP 4450 being locked to an incoming NICAM signal.
PRELIMINARY DATA SHEET
2.6. Surround Processing 2.6.1. Surround Processing Mode Surround sound processing is controlled by three functions: The "Decoder Matrix" defines which method is used to create a multichannel signal (L, C, R, S) out of a stereo input. The "Surround Reproduction" determines whether the surround signal "S" is fed to surround speakers. If no surround speaker is actually connected, it defines the method that is used to create surround effects. The "Center Mode" determines how the center signal "C" is to be processed. It can be left unmodified, distributed to left and right, discarded or high pass filtered, whereby the low pass signals are distributed to left and right.
2.3. Selection of Internal Processed Surround Signals Instead of having an multichannel input via the I2S_3 interface, a multichannel signal can be created by an internal Dolby Pro Logic decoder. In that case channels 3..8 of the multichannel input are replaced by the internally generated signals. 2.6.1.1. Decoder Matrix The Decoder Matrix allows three settings: - ADAPTIVE: The Adaptive Matrix is used for Dolby Surround Pro Logic. Even sound material not encoded in Dolby Surround will produce good surround effects in this mode. The use of the Adaptive Matrix requires a license from Dolby Laboratories (See License Notice on page 3). - PASSIVE: A simple fixed matrix is used for surround sound. - EFFECT: A fixed matrix that is used for mono sound and special effects. With Adaptive or Passive Matrix no surround signal is present in case of mono, moreover in Adaptive mode even the left and right output channels carry no signal (or just low frequency signals in case of Center Mode = NORMAL). If surround sound is still required for mono signals, the Effect Matrix can be used. This forces the surround channel to be active. The Effect Matrix can be used together with 3D-PANORAMA. The result will be a pseudo stereo effect or a broadened stereo image respectively.
2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (I2S input signals) to the desired output channels (Main, Aux, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the output channel matrix can be set to sound A (left mono), sound B (right mono), stereo, or mono (sound left and right).
2.5. Audio Baseband Processing 2.5.1. Main and Aux Outputs The following baseband features are implemented in the Main and Aux output channels: bass/treble, loudness, balance, and volume. A square wave beeper can be added to these outputs. The Main channel additionally supports an equalizer function (this is not simultaneously available with bass/treble).
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PRELIMINARY DATA SHEET
DPL 4519G
2.6.1.4. Useful Combinations of Surround Processing Modes In principle, "Decoder Matrix", "Surround Reproduction", and "Center Modes" are independent settings (all "Decoder Matrix" settings can be used with all "Surround Reproduction" and "Center Modes") but there are some combinations that do not create "good" sound. Useful combinations are
2.6.1.2. Surround Reproduction Surround sound can be reproduced with four choices: - REAR_SPEAKER: If there are any surround speakers connected to the system, this mode should be used. Useful loudspeaker combinations are (L, C, R, S) or (L, R, S). - FRONT_SPEAKER: If there is no surround speaker connected, this mode can be used. Surround information is mixed to left and right output but without creating the illusion of a virtual speaker. It is similar to stereo but an additional center speaker can be used. This mode should be used with the Adaptive decoder Matrix only. Useful loudspeaker combinations are (L, C, R) (Note: the surround output channel is muted). - PANORAMA: The surround information is mixed to left and right in order to create the illusion of a virtual surround speaker. Useful loudspeaker combinations are (L, C, R) or (L, R) (Note: the surround output channel is muted). - 3D-PANORAMA: Like PANORAMA with improved effect. This algorithm has been approved by the Dolby Laboratories for compliance with the "Virtual Dolby Surround" technology. Useful loudspeaker combinations are (L, C, R) or (L, R) (Note: the surround output channel is muted).
Surround Reproduction and Center Modes - REAR_SPEAKER: This mode is used if surround speakers are available. Useful center modes are NORMAL, WIDE, PHANTOM, and OFF. - FRONT_SPEAKER: This mode can be used if no surround speaker but a center speaker is connected. Useful center modes are NORMAL and WIDE. - PANORAMA or 3D-PANORAMA: No surround speaker used. Two (L and R) or three (L, R, and C) loudspeakers can be used. Useful center modes are NORMAL, WIDE, PHANTOM, and OFF.
Center Modes and Decoder Matrix - PHANTOM: Should only be used together with ADAPTIVE Decoder Matrix. - NORMAL and WIDE: Can be used together with any Surround Decoder Matrix. - OFF: This mode can be used together with the PASSIVE and EFFECT Decoder Matrix (no center speaker connected).
2.6.1.3. Center Modes Four center modes are supported: - NORMAL: small center speaker connected, L and R speakers have better bass capability. Center signal is high pass filtered. - WIDE: L, R, and C speakers all have good bass capability. - PHANTOM: No center speaker used. Center signal is distributed to L and R (Note: the center output channel C is muted). - OFF: No center speaker used. Center signal C is discarded (Note: the center output channel C is muted).
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2.6.2. Examples Table 2-1 shows some examples of how these modes can be used to configure the IC. The list is not intended to be complete, more modes are possible.
PRELIMINARY DATA SHEET
Table 2-1: Examples of Surround Configurations
Configurations
Speaker Configuration1)
Surround Processing Mode
Register (4Bhex) Decoder Matrix [15:8] Surround Reproduction [7:4] Center Mode [3:0]
Stereo Stereo
(L,R) - - -
Surround Modes as defined by Dolby Laboratories 2) Dolby Surround Pro Logic
(L,C,R,S) ADAPTIVE REAR_ SPEAKER REAR_ SPEAKER FRONT_ SPEAKER 3D_PANORAMA NORMAL WIDE PHANTOM
(L,R,S)
ADAPTIVE
Dolby 3 Stereo Virtual Dolby Surround
(L,C,R)
ADAPTIVE
NORMAL WIDE PHANTOM
(L,R)
ADAPTIVE
Surround Modes that use the Dolby Adaptive Matrix2) 3-Channel Virtual Surround Passive Matrix Surround Sound 4-Channel Surround 3-Channel Surround 2-Channel Micronas 3D Surround Sound (MSS) 3-Channel Micronas 3D Surround Sound (MSS) Special Effects Surround Sound 4-Channel Surround for mono 2-Channel Virtual Surround for mono 3-Channel Virtual Surround for mono
1) 2)
(L,C,R)
ADAPTIVE
3D_PANORAMA
NORMAL WIDE
(L,C,R,S)
PASSIVE
REAR_ SPEAKER REAR_ SPEAKER 3D_PANORAMA 3D_PANORAMA
NORMAL WIDE OFF
(L,R,S)
PASSIVE
(L,R) (L,C,R)
PASSIVE PASSIVE
OFF NORMAL WIDE
(L,C,R,S)
EFFECT
REAR_ SPEAKER 3D_PANORAMA 3D_PANORAMA
NORMAL WIDE OFF NORMAL WIDE
(L,R) (L,C,R)
EFFECT EFFECT
Speakers not in use are muted automatically. The implementation in products requires a license from Dolby Laboratories Licensing Corporation (see note on page 3).
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PRELIMINARY DATA SHEET
DPL 4519G
Great care has to be taken with systems that use one common subwoofer: A single loudspeaker cannot reproduce virtual sound locations. The crossover frequency must be lower than 120 Hz.
2.6.3. Application Tips for using 3D-PANORAMA 2.6.3.1. Sweet Spot Good results are only obtained in a rather close area along the middle axis between the two loudspeakers: the sweet spot. Moving away from this position degrades the effect.
2.6.3.4. Cabinet Requirements During listening tests at Dolby Laboratories, no resonances in the cabinet should occur.
2.6.3.2. Clipping For the test at Dolby Labs, it is very important to have no clipping effects even with worst case signals. The I2S-prescale register has to be set to values of max 10hex (16dec). This is sufficient in terms of clipping. However, it was found, that by reducing the prescale to a value lower than 16dec more convincing effects are generated in case of very high dynamic signals. A value of 10dec is a good compromise between overall volume and additional headroom. Test signals: sine sweep with 0 dBFS; L only, R only, L&R equal phase, L&R anti phase. Listening tests: Dolby Trailers (train trailer, city trailer, canyon trailer...) Good material to check for resonances are the Dolby Trailers or other dynamic sound tracks.
2.6.4. Input and Output Levels for Dolby Surround Pro Logic The nominal input level (input sensitivity) for the I2SInputs is -15 dBFS. The highest possible input level of 0 dBFS is accepted without internal overflow. The I2Sprescale value should be set to values of max 0 dB (16dec). With higher prescale values lower input sensitivities can be accommodated. A higher input sensitivity is not possible, because at least 15 dB headroom is required for every input according to the Dolby specifications. A full-scale left only input (0 dBFS) will produce a fullscale left only output (at 0 dB volume). The typical output level is 1.37 Vrms for DACM_L. The same holds true for right only signals (1.37 Vrms for DACM_R). A full-scale input level on both inputs (Lin=Rin=0 dBFS) will give a center only output with maximum level. A full-scale input level on both inputs (but Lin and Rin with inverted phases) will give a surround-only signal with maximum level. For reproducing Dolby Pro Logic according to its specifications, the center and surround outputs must be amplified by 3 dB with respect to the L and R output signals. This can be done in two ways: 1. By implementing 3 dB more amplification for center and surround loudspeaker outputs. 2. By always selecting volume for L and R 3 dB lower than center and surround. Method 1 is preferable, as method 2 lowers the achievable SNR for left and right signals by 3 dB.
2.6.3.3. Loudspeaker Requirements The loudspeakers used and their positioning inside the TV set will greatly influence the performance of the virtualizer. The algorithm works with the direct sound path. Reflected sound waves reduce the effect. So it's most important to have as much direct sound as possible, compared to indirect sound. To obtain the approval for a TV set, Dolby Laboratories require mounting the loudspeakers at the front of the set. Loudspeakers radiating to the side of the TV set will not produce convincing effects. Good directionality of the loudspeakers towards the listener is optimal. The virtualizer was specially developed for implementation in TV sets. Even for rather small stereo TV's, sufficient sound effects can be obtained. For small sets, the loudspeaker placement should be to the side of the CRT; for large screen sets (or 16:9 sets), mounting the loudspeakers below the CRT is acceptable (large separation is preferred, low frequency speakers should be outmost to avoid cancellation effects). Using external loudspeakers with a large stereo base will not create optimal effects. The loudspeakers should be able to reproduce a wide frequency range. The most important frequency range starts from 160 Hz and ranges up to 5 kHz.
2.7. SCART Signal Routing 2.7.1. SCART Out Select The SCART Output Select block includes full matrix switching facilities. The switches are controlled by the ACB user register (see page page 30).
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2.7.2. Stand-by Mode If the DPL 4519G is switched off by first pulling STANDBYQ low and then (after >1 s delay) switching off DVSUP and AVSUP, but keeping AHVSUP (`Standby'-mode), the SCART switches maintain their position and function. This allows the copying from selected SCART-inputs to SCART-outputs in the TV set's stand-by mode. In case of power on or starting from stand-by (see details on the power-up sequence in Fig. 4-19 on page 52), all internal registers except the ACB register (page 30) are reset to the default configuration (see Table 3-5 on page 17). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part (subaddress 12hex). By transmitting the ACB register first, the reset state can be redefined. 2.8. I2S Bus Interfaces The DPL 4519G has two kinds of interfaces: synchron master/slave input/output interfaces running on 48 kHz and an asynchron slave interface. The interfaces accept a variety of formats with different sample width, bit-orientation, and wordstrobe timing. All I2S options are set by means of the MODUS or I2S_CONFIG register. 2.8.1. Synchronous I2S-Interface(s) The synchronous I2S bus interface consists of the pins: - I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in PQFP80 package): I2S serial data input, 16, 18...32 bits per sample. - I2S_DA_OUT: I2S serial data output, 16, 18...32 bits per sample. - I2S_CL: I2S serial clock. - I2S_WS: I2S word strobe signal defines the left and right sample. If the DPL 4519G serves as the master on the I2S interface, the clock and word strobe lines are driven by the DPL 4519G. In this mode, only 16, 32 bits per sample can be selected. In slave mode, these lines are input to the DPL 4519G and the DPL 4519G clock is synchronized to 384 times the I2S_WS rate (48 kHz). An I2S timing diagram is shown in Fig. 4-21 on page 55.
PRELIMINARY DATA SHEET
2.8.2. Asynchronous I2S-Interface The asynchronous I2S slave interface allows the reception of digital audio signals with arbitrary sample rates from 5 to 50 kHz. The synchronization is performed by means of an adaptive sample rate converter. No oversampling clock is required. The following pins are used for the asynchronous I2S bus interface (serve only as input): - I2S_WS3 - I2S_CL3 - I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package). The interface accepts I2S-input streams with MSB first and with sample widths of 16,18...32 bits. With left/ right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the I2S CONFIGURATION register. 2.8.3. Multichannel I2S-Output Bit[0:1] of the I2S CONFIGURATION register (see page 20) switches the output to 8 channel multichannel output mode. The bit resolution per channel is 32 bit in master mode. While the first two channels can be selected on the source select matrix, channels 3-8 are always connected to the I2S_3 input channels 3-8. Both, master and slave mode is possible, as long as as the wordstrobe has only one positive edge per frame in slave mode. 2.8.4. Asynchronous Multichannel I2S-Input The DPL 4519G supports two kinds of asynchronous multichannel input: - the asynchronous I2S_3 interface can be switched to multichannel mode (bit [8] of the I2S CONFIGURATION register is set to 1. The number of channels must be even and less or equal eight. - All I2S input lines (I2S_DA_IN1, I2S_DA_IN2 and I2S_DA_IN3 in PQFP80 package) can be switched to asynchronous two channel mode (bit[2] set to 1 in the I2S CONFIGURATION register). The common clock is I2S_WS3 and I2S_CL3. No synchronous I2S interfaces are available in this mode.
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PRELIMINARY DATA SHEET
DPL 4519G
2.9. Digital Control I/O Pins The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page 30). This enables the controlling of external hardware switches or other devices via I2C-bus. The Modus Register can set the digital input/output pins to high impedance (see page 19). So the pins can be used as input. The current state can be read out of the STATUS register (see page page 21).
2.10. Clock PLL Oscillator and Crystal Specifications The DPL 4519G derives all internal system clocks from the 18.432 MHz oscillator. In I2S-slave mode of the synchronous interface, the clock is phase-locked to the corresponding source. For proper performance, the DPL clock oscillator requires a 18.432-MHz crystal. Note that for the phase-locked modes (I2S-slave), crystals with tighter tolerance are required. The asynchronous I2S3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances.
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3. Control Interface 3.1. I2C Bus Interface 3.1.1. Device and Subaddresses The DPL 4519G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the DPL 4519G device addresses. In order to allow up to three DPL or MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the DPL 4519G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table 3-1). Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section 3.1.4. for the I2C bus protocol and to Section 3.4. "Programming Tips" on page 34 for proposals of DPL 4519G I2C telegrams. See Table 3-2 for a list of available subaddresses. Besides the possibility of hardware reset, the DPL can also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus. Due to the internal architecture of the DPL 4519G, the IC cannot react immediately to an I2C request. The Table 3-1: I2C Bus Device Addresses
ADR_SEL Mode DPL device address Low (connected to DVSS) Write 80hex Read 81hex High (connected to DVSUP) Write 84hex Read 85hex
PRELIMINARY DATA SHEET
typical response time is about 0.3 ms. If the DPL cannot accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by "Wait" in Section 3.1.4. The maximum wait period of the DPL during normal operation mode is less than 1 ms.
3.1.2. Internal Hardware Error Handling In case of any internal hardware error (e.g. interruption of the power supply of the DPL), the DPL's wait period is extended to 1.8 ms. After this time period elapses, the DPL releases data and clock lines.
Indicating and solving the error status: To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The DPL can then be reset via the I2C bus by transmitting the reset condition to CONTROL.
Indication of reset: Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C bus is shown in Fig. 4-21 on page 55.
Left Open Write 88hex Read 89hex
Table 3-2: I2C Bus Subaddresses
Name CONTROL WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 10 11 12 13 Mode Read/Write Write Write Write Write Function Write: Software reset of DPL (see Table 3-3) Read: Hardware error status of DPL write address demodulator read address demodulator write address DSP read address DSP
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PRELIMINARY DATA SHEET
DPL 4519G
3.1.3. Description of CONTROL Register
Table 3-3: CONTROL as a Write Register
Name CONTROL Subaddress 00 hex Bit[15] (MSB) 1 : RESET 0 : normal Bits[14:0] 0
Table 3-4: CONTROL as a Read Register (only DPL 4519G-versions from A2 on)
Name CONTROL Subaddress 00 hex Bit[15] (MSB) Reset status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Bit[14] Internal hardware status: 0 : no error occured 1 : internal error occured Bits[13:0] not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be resetted.
3.1.4. Protocol Description Write to DSP
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P high low high low
Read from DSP
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low
Write to Control
S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low
Read from Control
S Wait write device address ACK 00hex ACK S read device address Wait ACK data-byte- ACK data-byte NAK P high low
Note: S = P= ACK = NAK = Wait =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= DPL, light gray) or master (= controller dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate `End of Read' or from DPL indicating internal error state I2C-Clock line is held low, while the DPL is processing the I2C command. This waiting time is max. 1 ms
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PRELIMINARY DATA SHEET
I2C_DA S I2C_CL
1 0 P
Fig. 3-1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.5. Proposals for General DPL 4519G I2C Telegrams 3.1.5.1. Symbols daw dar < > aa dd write device address (80hex, 84hex or 88hex) read device address (81hex, 85hex or 89hex) Start Condition Stop Condition Address Byte Data Byte
3.2. Start-Up Sequence: Power-Up and I2C Controlling After POWER ON or RESET (see Fig. 4-21), the IC is in an inactive state. All registers are in the reset position, the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary.
3.3. DPL 4519G Programming Interface 3.3.1. User Registers Overview
3.1.5.2. Write Telegrams

write to CONTROL register write data into demodulator write data into DSP
The DPL 4519G is controlled by means of user registers. The complete list of all user registers is given in the following tables. The registers are partitioned into two sections: 1. Subaddress 10hex for writing, 11hex for reading and
3.1.5.3. Read Telegrams
read data from CONTROL register read data from demodulator read data from DSP

2. Subaddress 12hex for writing, 13hex for reading. Write and read registers are 16-bit wide, whereby the MSB is denoted bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write registers, except MODUS and I2S CONFIGURATION, are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be accessed.
3.1.5.4. Examples
<80 00 80 00> <80 00 00 00> <80 12 00 08 08 20> <80 12 00 00 73 00>
RESET DPL statically Clear RESET Set Main channel source to I2S3 - L/R Set Main volume to 0 dB
More examples of typical application protocols are listed in Section 3.4. "Programming Tips" on page 34.
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PRELIMINARY DATA SHEET
DPL 4519G
Table 3-5: List of DPL 4519G Write Registers
Write Register Address (hex) Bits Description and Adjustable Range Reset See Page
I2C Subaddress = 10hex ; Registers are not readable MODUS I2S CONFIGURATION 00 30 00 40 [15:0] [15:0] I2S options, D_CTR_I/O modes Configuration of I2S format 00 00 00 00 19 20
I2C Subaddress = 12hex ; Registers are all readable by using I2C Subaddress = 13hex Volume Main channel 00 00 [15:8] [7:5] [4:0] Balance Main channel [L/R] Balance mode Main Bass Main channel Treble Main channel Loudness Main channel Loudness filter characteristic Volume Aux channel 00 06 00 02 00 03 00 04 00 01 [15:8] [7:0] [15:8] [15:8] [15:8] [7:0] [15:8] [7:5] [4:0] Volume SCART1 output channel Main source select Main channel matrix Aux source select Aux channel matrix SCART1 source select SCART1 channel matrix I S source select I2S channel matrix Prescale I2S3 00 11 00 12 00 13 00 14 00 16 00 20 00 21 00 22 00 23 00 24 00 25 00 2C
2
[+12 dB ... -114 dB, MUTE] 1/8 dB Steps must be set to 0 [0...100 / 100% and 100 / 0...100%] [-127...0 / 0 and 0 / -127...0 dB] [Linear / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [+12 dB ... -114 dB, MUTE] 1/8 dB Steps must be set to 0 [+12 dB ... -114 dB, MUTE] [I S1, I S2, I S3 ch1&2, I S3 ch3&4,...] [SOUNDA, SOUNDB, STEREO, MONO] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] [SOUNDA, SOUNDB, STEREO, MONO] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] [SOUNDA, SOUNDB, STEREO, MONO] [I S1, I S2, I S3 ch1&2, I S3 ch3&4,...] [SOUNDA, SOUNDB, STEREO, MONO] [00hex ... 7Fhex] [00hex ... 7Fhex] Bits [15:0] [00hex ... 7Fhex]/[00hex ... 7Fhex] [00hex ... 7Fhex] [BASS/TREBLE, EQUALIZER] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [0 dB ... -30 dB, mute]
2 2 2 2 2 2 2 2
MUTE 000bin 00000bin 100%/100% linear mode 0 dB 0 dB 0 dB NORMAL MUTE 000bin 00000bin MUTE undefined SOUNDA undefined SOUNDA undefined SOUNDA undefined SOUNDA 10hex 10hex 00hex 00/00hex 10hex BASS/TREB 0 dB 0 dB 0 dB 0 dB 0 dB 0 dB
24
25
26 27 28
24
00 07 00 08
[15:8] [15:8] [7:0]
29 23 23 23 23 23 23 23 23 21 21 30 30 21 26 27 27 27 27 27 29
00 09
[15:8] [7:0]
00 0A
[15:8] [7:0]
00 0B
[15:8] [7:0] [15:8] [15:8] [15:0] [15:0] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8]
Prescale I2S2 ACB: SCART Switches a. D_CTR_I/O Beeper Prescale I2S1 Mode tone control Equalizer Main ch. band 1 Equalizer Main ch. band 2 Equalizer Main ch. band 3 Equalizer Main ch. band 4 Equalizer Main ch. band 5 Subwoofer level adjust
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Table 3-5: List of DPL 4519G Write Registers, continued
Write Register Balance Aux channel [L/R] Balance mode Aux Bass Aux channel Treble Aux channel Loudness Aux channel Loudness filter characteristic I S3 Resorting Surround source select Surround channel matrix Spatial effect for surround processing Virtual surround effect strength Decoder matrix Surround reproduction Center mode Surround delay Noise Generator 00 4C 00 4D 00 49 00 4A 00 4B
2
PRELIMINARY DATA SHEET
Address (hex) 00 30
Bits [15:8] [7:0]
Description and Adjustable Range [0...100 / 100% and 100 / 0...100%] [-127...0 / 0 and 0 / -127...0 dB] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] through, straight eight, l/r eight, l/r six, l/r four, 2ch through [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] [SOUNDA, SOUNDB, STEREO, MONO] [0% - 100%] [0% - 100%] [ADAPTIVE/PASSIVE/EFFECT] [REAR_SPEAKER/FRONT_SPEAKER/PANORAMA/ 3D_PANORAMA] [PHANTOM/NORMAL/WIDE/OFF] [5...31ms] [NOISEL, NOISEC, NOISER, NOISES]
Reset 100 %/100 % linear mode 0 dB 0 dB 0 dB NORMAL 00hex undefined SOUNDA 00hex 00hex 00hex 0hex 0hex 00hex 00hex
See Page 25
00 31 00 32 00 33
[15:8] [15:8] [15:8] [7:0]
26 27 28
00 36 00 48
[15:8] [15:8] [7:0] [15:8] [15:8] [15:8] [7:4] [3:0] [15:0] [15:0]
22 23 23 31 31 32 32 32 32 32
Table 3-6: List of DPL 4519G Read Registers
Read Register Address (hex) Bits Description and Adjustable Range See Page
I2C Subaddress = 11hex ; Registers are not writable STATUS
2
02 00
[15:0]
Monitoring of settings e.g. D_CTR_I/O
21
I C Subaddress = 13hex ; Registers are not writable DPL hardware version code DPL major revision code DPL product code DPL ROM version code 00 1F 00 1E [15:8] [7:0] [15:8] [7:0] [00hex ... FFhex] [00hex ... FFhex] [00hex ... FFhex] [00hex ... FFhex] 33 33 33 33
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DPL 4519G
3.3.2. Description of User Registers 3.3.2.1. Write Registers on I2C Subaddress 10hex Table 3-7: Write Registers on I2C Subaddress 10hex Register Address MODUS 00 30hex MODUS Register bit[15:8] bit[7] bit[6] 0 1 bit[5] bit[4] bit[3] 0 1 bit[2:0] 0 0/1 0/1 0 0/1 undefined, must be 0 active/tristate state of audio clock output pin AUD_CL_OUT word strobe alignment (synchronous I2S) WS changes at data word boundary WS changes one clock cycle in advance master/slave mode of I2S interface active/tristate state of I2S output pins state of digital output pins D_CTR_I/O_0 and _1 active: D_CTR_I/O_0 and _1 are output pins (can be set by means of the ACB register) tristate: D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) undefined, must be 0 MODUS Function Name
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Table 3-7: Write Registers on I2C Subaddress 10hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
I2S CONFIGURATION 00 40hex I2S CONFIGURATION Register I2S31) bit[11] bit[10] I2S data alignment (must be 0 if bit[2] = 1) 0/1 left/right aligned wordstrobe polarity (must be 0 if bit[2] = 1) 1 0 = right, 1 = left 0 1 = right, 0 = left wordstrobe alignment (asynchronous I2S_3) 0 WS changes at data word boundary 1 WS changes one clock cycle in advance Sample Mode 0/1 Two/Multi sample Word length of each data packet = (n-2)/2 bit[3]=0, bit[8]=1 (multi-sample input mode) 0111 16 bit 1000 18 bit ... 1111 32 bit bit[3]=0, bit[8]=0 (two-sample input mode) xxxx 16...32 bit, 18-bit valid bit[3]=1, bit[8]=1 (multi-sample output mode) 1111 32 bit bit[3]=1, bit[8]=0 (two-sample output mode) 0111 16 bit 1111 32 bit bit[3] I2S3 Mode 1 output (I2S3 CL/WS active) 0 input (I2S3 CL/WS tristate) I2S3_MODE I2S3_ALIGN I2S3_WS_POL I2S_CONFIG
bit[9]
I2S3_WS_MODE
bit[8] bit[7:4]
I2S3_MSAMP I2S3_MBIT
I2S1/2/3 bit[2] I2S1/2/3 Timing 1 I2S3 timing for all I2S inputs (1/2/3) 0 default mode I2S_TIMING
I2S Out bit[1:0] I2S_CL frequency and I2S_DA_OUT sample length 00 2 * 16 bit (1.536 MHz Clk) 01 2 * 32 bit (3.072 MHz Clk) 10 8 * 32 bit (12.288 MHz Clk)
1)
I2S_CL3 frequency depends on bit[8] and bits[7:4] as follows: [8] = 0, [7:4] = 0111 f = fs*(2*16) [8] = 0, [7:4] = else f = fs*(2*32) [8] = 1 f = fs*(8*32)
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PRELIMINARY DATA SHEET
DPL 4519G
3.3.2.2. Read Registers on I2C Subaddress 11hex Table 3-8: Read Registers on I2C Subaddress 11hex Register Address 02 00hex Function STATUS Register Contains the status of the D_CTR_I/O pins bit[15:5] bit[4] bit[3] bit[2:0] 0/1 0/1 undefined low/high level of digital I/O pin D_CTR_I/O_1 low/high level of digital I/O pin D_CTR_I/O_0 undefined Name STATUS
3.3.2.3. Write Registers on I2C Subaddress 12hex Table 3-9: Write Registers on I2C Subaddress 12hex Register Address Function Name
PREPROCESSING 00 16hex 00 12hex 00 11hex I2S1 Prescale I2S2 Prescale I2S3 Prescale Defines the prescale value for digital I2S input signals bit[15:8] 00hex 10hex 7Fhex off 0 dB gain (recommendation) +18 dB gain (maximum gain) PRE_I2S1 PRE_I2S2 PRE_I2S3
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Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
I2S3 RESORTING MATRIX 00 36hex
I2S3 Resorting Matrix (not mentioned bit combinations must not be used) Resorting of multichannel inputs bit[15:8] 0000hex : 8 channel, "through" 1,2,3,4,5,6,7,8 Lt,Rt Lt,Rt,Lvirtual,Rvirtual 1,2,3,4,5,6,7,8 Lt,Rt,--,--,--,--,--,-Lt,Rt,Lvirtual,Rvirtual,--,--,--,-7,8,1,2,3,4,5,6 Lt,Rt,L,R,SL,SR,C,LFE I2S3_Sort
0001hex : 8 channel, "straight eight" 1,2,3,4,5,6,7,8 L,R,SL,SR,C,LFE,Lt,Rt
0002hex : 8 channel, "left/right eight", "MAS 3528E" 1,2,3,4,5,6,7,8 4,8,1,5,2,6,3,7 Lt,Rt,L,R,SL,SR,C,LFE L,SL,C,Lt,R,SR,LFE,Rt 0003hex : 6 channel, "left/right six" 1,2,3,4,5,6 L,SL,C,R,SR,LFE -,-,1,4,2,5,3,6 --,--,L,R,SL,SR,C,LFE
0004hex : 4 channel, "left/right four", "External ProLogic" 1,2,3,4 -,-,1,3,4,4,2,L,C,R,S --,--,L,R,SL,SR,C,-0010hex : 2 channel, "through"; "Internal ProLogic" 1,2 1,2,+,+,+,+,+,+ Lt,Rt,LPL,RPL,SPL,SPL,CPL,SUBPL Lt,Rt
"+": channel will be replaced by internally generated signal "XPL": internally generated signal
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DPL 4519G
Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
SOURCE SELECT AND OUTPUT CHANNEL MATRIX 00 08hex 00 09hex 00 0Ahex 00 0Bhex 00 48hex Source for: Main Output Aux Output SCART1 DA Output I2S Output Surround Processing bit[15:8] 5 6 7 8 9 10
1)
SRC_MAIN SRC_AUX SRC_SCART1 SRC_I2S SRC_DPL
I2S1 input I2S2 input I2S3 input channels 1&2 (e.g. Lt,Rt)1) I2S3 input channels 3&4 (e.g. L,R)1) or Pro Logic processed L, R I2S3 input channels 5&6 (e.g. SL,SR)1) or Pro Logic processed S, S (both channels same signal) I2S3 input channels 7&8 (e.g. C,SUB)1) or Pro Logic processed C, SUB
exemplary channel assignment in a Micronas digital multichannel sound system with MAS 3528E and MSP 4450G. 00 08hex 00 09hex 00 0Ahex 00 0Bhex 00 48hex Channel Matrix for: Main Output Aux Output SCART1 DA Output I2S Output Surround Processing bit[7:0] 00hex 10hex 20hex 30hex Sound A Mono (or Left Mono) Sound B Mono (or Right Mono) Stereo (transparent mode) Mono (L+R)/2 MAT_MAIN MAT_AUX MAT_SCART1 MAT_I2S MAT_DPL
Usually the matrix modes should be set to "Stereo" (transparent).
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Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
MAIN AND AUX PROCESSING 00 00hex 00 06hex Volume Main Volume Aux bit[15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex +11 dB 7Ehex ... +1 dB 74hex 0 dB 73hex -1 dB 72hex ... -113 dB 02hex -114 dB 01hex Mute (reset condition) 00hex Fast Mute FFhex higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table not used must be set to 0 VOL_MAIN VOL_AUX
bit[7:5]
bit[4:0]
With large scale input signals, positive volume settings may lead to signal clipping. The DPL 4519G Main and Aux Volume function is divided into a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted.
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PRELIMINARY DATA SHEET
DPL 4519G
Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address 00 01hex 00 30hex Function Balance Main Channel Balance Aux Channel bit[15:8] Linear Mode Left muted, Right 100% 7Fhex Left 0.8%, Right 100% 7Ehex ... Left 99.2%, Right 100% 01hex Left 100%, Right 100% 00hex Left 100%, Right 99.2% FFhex ... Left 100%, Right 0.8% 82hex Left 100%, Right muted 81hex Logarithmic Mode Left -127 dB, Right 0 dB 7Fhex Left -126 dB, Right 0 dB 7Ehex ... Left -1 dB, Right 0 dB 01hex Left 0 dB, Right 0 dB 00hex Left 0 dB, Right -1 dB FFhex ... Left 0 dB, Right -127 dB 81hex Left 0 dB, Right -128 dB 80hex Balance Mode linear 0hex logarithmic 1hex Name BAL_MAIN BAL_AUX
bit[15:8]
bit[3:0]
Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected.
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Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address 00 20hex Function Tone Control Mode Main Channel bit[15:8] 00hex FFhex bass and treble is active equalizer is active
PRELIMINARY DATA SHEET
Name TONE_MODE
Defines whether Bass/Treble or Equalizer is activated for the Main channel. Bass/Treble and Equalizer cannot work simultaneously. If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa. 00 02hex 00 31hex Bass Main Channel Bass Aux Channel bit[15:8] normal range +12 dB 60hex +11 dB 58hex ... +1 dB 08hex 0 dB 00hex -1 dB F8hex ... -11 dB A8hex -12 dB A0hex extended range +20 dB 7Fhex +18 dB 78hex +16 dB 70hex +14 dB 68hex BASS_MAIN BASS_AUX
bit[15:8]
Higher resolution is possible: an LSB step in the normal range results in a gain step of about 1/8 dB, in the extended range about 1/4 dB. With positive bass settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain.
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DPL 4519G
Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address 00 03hex 00 32hex Function Treble Main Channel Treble Aux Channel bit[15:8] 78hex 70hex ... 08hex 00hex F8hex ... A8hex A0hex +15 dB +14 dB +1 dB 0 dB -1 dB -11 dB -12 dB Name TREB_MAIN TREB_AUX
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive treble settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. 00 21hex 00 22hex 00 23hex 00 24hex 00 25hex Equalizer Main Channel Band 1 (below 120 Hz) Equalizer Main Channel Band 2 (center: 500 Hz) Equalizer Main Channel Band 3 (center: 1.5 kHz) Equalizer Main Channel Band 4 (center: 5 kHz) Equalizer Main Channel Band 5 (above: 10 kHz) bit[15:8] 60hex 58hex ... 08hex 00hex F8hex ... A8hex A0hex +12 dB +11 dB +1 dB 0 dB -1 dB -11 dB -12 dB EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive equalizer settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain.
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Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address 00 04hex 00 33hex Function Loudness Main Channel Loudness Aux Channel bit[15:8] Loudness Gain +17 dB 44hex +16 dB 40hex ... +1 dB 04hex 0 dB 00hex Loudness Mode normal (constant volume at 1 kHz) 00hex Super Bass (constant volume at 2 kHz) 04hex
PRELIMINARY DATA SHEET
Name LOUD_MAIN LOUD_AUX
bit[7:0]
Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1-kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.
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DPL 4519G
Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address 00 2Chex Function Subwoofer Level Adjustment bit[15:8] 00hex FFhex ... E3hex E2hex ... 80hex 0 dB -1 dB -29 dB -30 dB Mute Name SUBW_LEVEL
SCART OUTPUT CHANNEL 00 07hex Volume SCART1 Output Channel bit[15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex +11 dB 7Ehex ... +1 dB 74hex 0 dB 73hex -1 dB 72hex ... -113 dB 02hex -114 dB 01hex Mute (reset condition) 00hex higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table 01hex this must be 01hex VOL_SCART1
bit[7:5]
bit[4:0]
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Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
SCART SWITCHES AND DIGITAL I/O PINS 00 13hex ACB Register Defines the level of the digital output pins and the position of the SCART switches bit[15] bit[14] bit[13:5] 0/1 0/1 low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) ACB_REG
SCART1 Output Select xx00xx x0x SCART3 input to SCART1 output (RESET position) xx01xx x0x SCART2 input to SCART1 output xx10xx x0x MONO input to SCART1 output xx11xx x0x SCART1 DA to SCART1 output xx01xx x1x SCART1 input to SCART1 output xx10xx x1x SCART4 input to SCART1 output xx11xx x1x mute SCART1 output SCART2 Output Select 00xxxx 0xx SCART1 DA to SCART2 output (RESET position) 01xxxx 0xx SCART1 input to SCART2 output 10xxxx 0xx MONO input to SCART2 output 01xxxx 1xx SCART2 input to SCART2 output 10xxxx 1xx SCART3 input to SCART2 output 11xxxx 1xx SCART4 input to SCART2 output 11xxxx 0xx mute SCART2 output
bit[13:5]
The RESET position becomes active at the time of the first write transmission on the control bus to the audio processing part. By writing to the ACB register first, the RESET state can be redefined. BEEPER 00 14hex Beeper Volume and Frequency bit[15:8] Beeper Volume off 00hex maximum volume 7Fhex Beeper Frequency 16 Hz (lowest) 01hex 1 kHz 40hex 4 kHz FFhex BEEPER
bit[7:0]
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
SURROUND PROCESSING 00 49hex Spatial Effects for Surround Processing bit[15:8] Spatial Effect Strength Enlargement 100% 7Fhex Enlargement 50% 3Fhex ... Enlargement 1.5% 01hex Effect off 00hex 00hex must be 0 SUR_SPAT
bit[7:0]
Increases the perceived basewidth of the reproduced left and right front channels. Recommended value: 50% = 40hex. 00 4Ahex Virtual Surround Effect Strength bit[15:8] Virtual Surround Effect Strength Effect 100% 7Fhex Effect 50% 3Fhex ... 01hex 00hex bit[7:0] 00hex Effect 1.5% Effect off must be 0 SUR_3DEFF
Strength of the surround effect in PANORAMA or 3D-PANORAMA mode. In other Surround Reproduction Modes this value must be set to 0. Recommended value: 66% = 54hex.
Micronas
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DPL 4519G
Table 3-9: Write Registers on I2C Subaddress 12hex, continued Register Address 00 4Bhex Function Surround Processing Mode bit[15:8]
PRELIMINARY DATA SHEET
Name SUR_MODE DEC_MAT
Decoder Matrix ADAPTIVE (for Dolby Surround Pro Logic and Virtual 00hex Surround) PASSIVE (for MSS, Micronas Surround Sound) 10hex EFFECT (used for special effects and monophonic 20hex signals) Surround Reproduction 0hex 3hex REAR_SPEAKER: The surround signal is reproduced by rear speakers. FRONT_SPEAKER: The surround signal is redirected to the front channels. There is no physical rear speaker connected. PANORAMA: The surround signal is processed and redirected to the left and right front speakers in order to create the illusion of a virtual rear speaker, although no physical rear speaker is connected. 3D-PANORAMA: The surround signal is processed and redirected to the left and right front speakers in order to create the illusion of a virtual rear speaker, although no physical rear speaker is connected.
bit[7:4]
SUR_REPRO
5hex
6hex
bit[3:0]
Center Mode 0hex 1hex 2hex 3hex PHANTOM mode (no Center speaker connected) NORMAL mode (small Center speaker) WIDE mode (large Center speaker) OFF mode (Center output of the Surround Decoder is discarded. Useful only in special effect modes)
C_MODE
00 4Chex
Surround Delay bit[15:8] 05hex 06hex ... 1Fhex 00hex 5 ms delay in surround path (lowest) 6 ms delay in surround path 31 ms delay in surround path (highest)) must be 0
SUR_DELAY
bit[7:0]
For Dolby Surround Pro Logic designs, only 20 ms fixed or 15-30 ms variable delay must be used. This register has no effect in 3D-PANORAMA and PANORAMA mode. 00 4Dhex Noise Generator bit[15:8] bit[7:0] 00hex 80hex A0hex B0hex C0hex D0hex Noise generator off Noise generator on Noise on left channel Noise on center channel Noise on right channel Noise on surround channel SUR_NOISE
Determines the active channel for the noise generator.
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
3.3.2.4. Read Registers on I2C Subaddress 13hex Table 3-10: Read Registers on I2C Subaddress 13hex Register Address Function Name
DPL 4519G VERSION READOUT Registers 00 1Ehex DPL Hardware Version Code bit[15:8] 01hex DPL 4519G-A1 DPL_HARD
A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint. DPL Family Code bit[7:4] 3hex DPL 4519G-A1 DPL_REVISION DPL_FAMILY
DPL Major Revision Code bit[3:0] 00 1Fhex 7hex DPL 4519G-A1
DPL Product Code bit[15:8] 13hex DPL 4519G - A1
DPL_PRODUCT
By means of the DPL-Product Code, the control processor is able to decide which TV sound standards have to be considered. DPL ROM Version Code bit[7:0] 41hex 42hex DPL 4519G - A1 DPL 4519G - A2 DPL_ROM
A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new DPL 4519G versions according to this number.
Micronas
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DPL 4519G
3.4. Programming Tips This section describes the preferred method for initializing the DPL 4519G. The initialization is grouped into four sections: analog signal path, input processing for I2S, and output processing. See Fig. 2-1 on page 7 for a complete signal flow.
PRELIMINARY DATA SHEET
3.5. Examples of Minimum Initialization Codes Initialization of the DPL 4519G according to these listings reproduces sound of the selected standard on the Main output. All numbers are hexadecimal. The examples have the following structure: 1. Perform an I2C controlled reset of the IC. 2. Write MODUS register
SCART Signal Path 1. Select the source for each analog SCART output with the ACB register. I2S Inputs 1. Select preferred prescale for I2S inputs (set to 0 dB after RESET). 2. Select I2S3 Resorting matrix according to the channel order of your decoding device (e.g. for MAS 3528E chose mode 02hex) Output Channels 1. Select the source channel and matrix for each output. 2. Set audio baseband features 3. Select volume for each output.
3. Set Source Selection for Main channel (with matrix set to STEREO). 4. Set Volume Main channel to 0 dB.
3.5.1. Micronas Dolby Digital chipset (with MAS 3528E)
<84 00 80 00> <84 00 00 00> <84 10 00 30 00 20> <84 10 00 40 01 F2> <84 12 00 36 00 02> <84 12 00 0B 07 20> <84 12 00 08 08 20> <84 12 00 00 73 00>
// MODUS-Register: I2S slave // I2S-config-Register // I2S3 Resorting matrix, Mode 2 // Source Sel. I2S_out = I2S3 - Lt/Rt // Source Sel. Main_out = I2S3 - L/R // Main Volume 0 dB // Softreset
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
4. Specifications 4.1. Outline Dimensions
23 x 0.8 = 18.4 0.1 0.8
0.17 0.04 64 65 41 40
80 1 23.2 0.15 24
25 1.3 0.05 2.7 0.1 3 0.2 0.1 20 0.1
SPGS705000-3(P80)/1E
Fig. 4-1: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm
15 x 0.5 = 7.5 0.1 0.145 48 49 12 0.2 33 15 x 0.5 = 7.5 0.1 32 10 0.1 0.5
0.055
0.5
1.75
64 1 1.75 12 0.2 16
17
1.4 0.05 1.5 0.1 0.1 10 0.1
0.22 0.05
D0025/3E
Fig. 4-2: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions in mm
Micronas
15 x 0.8 = 12.0 0.1
17.2 0.15
0.37 0.04
14 0.1
0.8
35
DPL 4519G
PRELIMINARY DATA SHEET
SPGS703000-1(P64)/1E
64
33
1
32
57.7 0.1
0.8 0.2 3.8 0.1
19.3 0.1 18 0.05
0.28 0.06 3.2 0.2 1 0.05 1.778 0.48 0.06 31 x 1.778 = 55.1 0.1 20.3 0.5
Fig. 4-3: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
4.2. Pin Connections and Short Descriptions NC = not connected (leave vacant for future compatibility reasons) TP = Test Pin (leave vacant - pin is used for production test only) LV = leave vacant X = obligatory; connect as described in application circuit diagram AHVSS: connect to AHVSS
Pin No.
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25
64 1 2 3 4 5 6 7 8 9 - - 10 - - 11 12 - 13 14 15 16 - - 17 18
8 9 10 11 12 13 14 15 16 17 - - 18 - - 19 20 - 21 22 23 24 - - 25 26
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP TP TP DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2/3 I2S_DA_IN2 NC I2S_CL3 I2S_WS3 RESETQ I2S_DA_IN3 NC DACA_R DACA_L OUT OUT IN IN IN IN IN IN IN/OUT IN/OUT IN/OUT IN/OUT OUT IN
LV X X LV LV LV LV LV LV LV X X X X X X LV LV LV LV LV X LV LV LV LV
Not connected I2C clock I2C data I2S clock I2S word strobe I2S data output I2S1 data input Test pin Test pin Test pin Digital power supply +5 V Digital power supply +5 V Digital power supply +5 V Digital ground Digital ground Digital ground I2S2/3-data input
PQFP80: pin 22 separate I2S_DA_IN3
Not connected I2S3 clock I2S3 word strobe Power-on-reset I2S3-data input Not connected Aux out, right Aux out, left
Micronas
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DPL 4519G
PRELIMINARY DATA SHEET
Pin No.
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
19 20 21 22 23 24 - 25 26 27 28 29 30 31 32 - - - 33 34 - 35 36 37 38 39 40 41 42 43 44
27 28 29 30 31 32 - 33 34 35 36 37 38 39 40 - - - 41 42 - 43 44 45 46 47 48 49 50 51 52
VREF2 DACM_R DACM_L NC DACM_SUB NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M NC NC AHVSS AHVSS AGNDC NC SC4_IN_L SC4_IN_R ASG SC3_IN_L SC3_IN_R ASG SC2_IN_L SC2_IN_R ASG SC1_IN_L IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT
X LV LV LV LV LV LV LV LV X LV LV X X X LV LV X X X LV LV LV AHVSS LV LV AHVSS LV LV AHVSS LV
Reference ground 2 Loudspeaker out, right Loudspeaker out, left Not connected Subwoofer output Not connected Not connected SCART output 2, right SCART output 2, left Reference ground 1 SCART output 1, right SCART output 1, left Volume capacitor AUX Analog power supply 8.0 V Volume capacitor MAIN Not connected Not connected Analog ground Analog ground Analog reference voltage Not connected SCART 4 input, left SCART 4 input, right Analog Shield Ground SCART 3 input, left SCART 3 input, right Analog Shield Ground SCART 2 input, left SCART 2 input, right Analog Shield Ground SCART 1 input, left
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Pin No.
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
45 46 - 47 - 48 - - - 49 50 51 52 53 54 55 56 57 - 58 59 60 61 62 63
53 54 - 55 - 56 - - - 57 58 59 60 61 62 63 64 1 - 2 3 4 5 6 7
SC1_IN_R NC NC MONO_IN AVSS AVSS NC NC AVSUP AVSUP NC NC NC TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
IN
LV LV LV
SCART 1 input, right Not connected Not connected Mono input Analog ground Analog ground Not connected Not connected Analog power supply +5 V Analog power supply +5 V Not connected Not connected Not connected Test pin Crystal oscillator Crystal oscillator (See also 4.3.
Pin descriptions)
IN
LV X X LV LV X X LV LV LV
IN IN OUT
AVSS X X / LV LV
Test pin Audio clock output (18.432 MHz) Not connected Not connected Not connected D_CTR_I/O_1 D_CTR_I/O_0 I2C Bus address select Stand-by (low-active)
OUT
LV LV LV LV
IN/OUT IN/OUT IN IN
LV LV X X
Micronas
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DPL 4519G
4.3. Pin Descriptions Pin numbers refer to the 80-pin PQFP package Pin 1, NC - Pin not connected. Pin 2, I2C_CL - I2C Clock Input/Output (Fig. 4-8) Via this pin, the I2C-bus clock signal has to be supplied. The signal can be pulled down by the DPL in case of wait conditions. Pin 3, I2C_DA - I2C Data Input/Output (Fig. 4-8) Via this pin, the I2C-bus data is written to or read from the DPL. Pin 4, I2S_CL - I2S Clock Input/Output (Fig. 4-11) Clock line for the I2S bus. In master mode, this line is driven by the DPL; in slave mode, an external I2S clock has to be supplied. Pin 5, I2S_WS - I2S Word Strobe Input/Output (Fig. 4-11) Word strobe line for the I2S bus. In master mode, this line is driven by the DPL; in slave mode, an external I2S word strobe has to be supplied. Pin 6, I2S_DA_OUT1 - I2S Data Output (Fig. 4-7) Output of digital serial sound data of the DPL on the I2S bus. Pin 7, I2S_DA_IN1 - I2S Data Input 1 (Fig. 4-9) First input of digital serial sound data to the DPL via the I2S bus. Pin 8, 9, 10, TP- Test pins Pins 11, 12, 13, DVSUP* - Digital Supply Voltage Power supply for the digital circuitry of the DPL. Must be connected to a power supply. Pins 14, 15, 16, DVSS* - Digital Ground Ground connection for the digital circuitry of the DPL. Pin 17, I2S_DA_IN2 - I2S Data Input 2 (Fig. 4-9) Second input of digital serial sound data to the DPL via the I2S bus. In all packages except PQFP-80-pin this pin is also connected to the asynchronous I2S interface 3. Pins 18, NC - Pin not connected. Pins 19, I2S_CL3 - I2S Clock Input (Fig. 4-9) Clock line for the I2S bus. Since only a slave mode is available an external I2S clock has to be supplied. Pins 20, I2S_WS3 - I2S Word Strobe Input (Fig. 4-9) Word strobe line for the I2S bus. Since only a slave mode is available an external I2S word strobe has to be supplied.
PRELIMINARY DATA SHEET
Pin 21, RESETQ - Reset Input (Fig. 4-9) In the steady state, high level is required. A low level resets the DPL 4519G. Pin 22, I2S_DA_IN3 - I2S Data Input 3 (Fig. 4-9) Asynchronous input of digital serial sound data to the DPL via the I2S bus. Pins 23, NC - Pin not connected. Pins 24, 25, DACA_R/L - Aux Outputs (Fig. 4-16) Output of the aux signal. A 1 nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected aux volume. Pin 26, VREF2 - Reference Ground 2 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF2 serves as a clean ground and should be used as the reference for analog connections to the Main and AUX outputs. Pins 27, 28, DACM_R/L - Main Outputs (Fig. 4-16) Output of the Main signal. A 1 nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected Main volume. Pin 29 NC - Pin not connected. Pin 30, DACM_SUB - Subwoofer Output (Fig. 4-16) Output of the subwoofer signal. A 1-nF capacitor to AHVSS must be connected to this pin. Due to the low frequency content of the subwoofer output, the value of the capacitor may be increased for better suppression of high-frequency noise. The DC offset on this pin depends on the selected Main volume. Pins 31, 32 NC - Pin not connected. Pins 33, 34, SC2_OUT_R/L - SCART2 Outputs (Fig. 4-18) Output of the SCART2 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled. Pin 35, VREF1 - Reference Ground 1 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 36, 37, SC1_OUT_R/L - SCART1 Outputs (Fig. 4-18) Output of the SCART1 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled.
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Pin 55, ASG* - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 56, 57 SC1_IN_L/R - SCART1 Inputs (Fig. 4-15) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC-coupled. Pin 58, NC - Pin not connected
Pin 38, CAPL_A - Volume Capacitor Aux (Fig. 4-13) A 10-F capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1-F if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pin 39, AHVSUP* - Analog Power Supply High Voltage Power is supplied via this pin for the analog circuitry of the DPL. This pin must be connected to the +8 V supply. (+5 V-operation is possible with restrictions in performance) Pin 40, CAPL_M - Volume Capacitor Loudspeakers (Fig. 4-13) A 10-F capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1 F if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pins 41, 42, NC - Pins not connected.
Pin 59, NC - Pin not connected. Pin 60 MONO_IN - Mono Input (Fig. 4-15) The analog mono input signal is fed to this pin AC-coupled. Pins 61, 62, AVSS* - Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the DPL. Pins 63, 64, NC - Pins not connected. Pins 65, 66, AVSUP* - Analog Power Supply Voltage Power is supplied via this pin for the analog IF input circuitry of the DPL. This pin must be connected to the +5 V supply. Pin 67, 68, 69, NC - Pin not connected.
Pins 43, 44, AHVSS* - Ground for Analog Power Supply High Voltage Ground connection for the analog circuitry of the DPL. Pin 45, AGNDC - Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry. It must be connected to the VREF pins with a 3.3-F and a 100-nF capacitor in parallel. This pins shows a DC level of typically 3.73 V. Pin 46, NC - Pin not connected. Pins 47, 48, SC4_IN_L/R - SCART4 Inputs (Fig. 4-15) The analog input signal for SCART4 is fed to this pin. Analog input connection must be AC-coupled. Pin 49, ASG* - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 50, 51, SC3_IN_L/R - SCART3 Inputs (Fig. 4-15) The analog input signal for SCART3 is fed to this pin. Analog input connection must be AC-coupled. Pin 52, ASG* - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 53, 54 SC2_IN_L/R - SCART2 Inputs (Fig. 4-15) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC-coupled.
Pin 70, TESTEN - Test Enable Pin (Fig. 4-9) This pin enables factory test modes. For normal operation, it must be connected to ground. Pins 71, 72 XTAL_IN, XTAL_OUT - Crystal Input and Output Pins (Fig. 4-12) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated capacitances. An external clock can be fed into XTAL_IN (leave XTAL_OUT vacant in this case). The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. Pin 73, TP - This pin is needed for factory tests. For normal operation, it must be left vacant. Pin 74, AUD_CL_OUT - Audio Clock Output (Fig. 4-12) This is the 18.432 MHz main clock output. Pins 75, 76, NC - Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 - Digital Control Input/ Output Pins (Fig. 4-11) General purpose input/output pins.
Micronas
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DPL 4519G
Pin 79, ADR_SEL - I2C Bus Address Select (Fig. 4-10) This pin selects the device address for the DPL. (see Table 3-1). Pin 80, STANDBYQ - Stand-by In normal operation, this pin must be High. If the DPL is switched to `Stand-by'-mode, the SCART switches maintain their position and function. (see Section 2.7.2.)
PRELIMINARY DATA SHEET
* Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 F. The capacitor with the lowest value should be placed nearest to the pins. The ASG pins should be connected as closely as possible to the IC ground. They are intended for leading with the SCART signals as shield lines and should not be connected to ground at the SCART-connector again.
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
4.4. Pin Configurations
SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R NC NC MONO_IN AVSS AVSS NC NC
ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC
AVSUP AVSUP NC NC NC TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L
DPL 4519G
33 32 31 30 29 28 27 26
25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 NC NC NC DVSUP DVSUP NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP NC
DACA_R
I2S_DA_IN3 RESETQ I2S_WS3 I2S_CL3
Fig. 4-4: 80-pin PQFP package
Micronas
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DPL 4519G
PRELIMINARY DATA SHEET
SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R NC MONO_IN AVSS
ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSUP NC NC NC TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 C_CTR_I/O_0 ADR_SEL STANDBYQ NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP TP TP NC I2S_DA_IN2/3 DVSS DVSUP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RESETQ I2S_WS3 I2S_CL3 32 31 30 29 28 27 26 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R
DPL 4519G
25 24 23 22 21 20 19 18 17
Fig. 4-5: 64-pin PLQFP package
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Micronas
PRELIMINARY DATA SHEET
DPL 4519G
4.5. Pin Circuits
AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 TP TP TP DVSUP DVSS I2S_DA_IN2/3 NC I2S_CL3 I2S_WS3 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC
1 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
TP XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP AVSS MONO_IN NC SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
Pin numbers refer to the PQFP80 package. DVSUP P N GND Fig. 4-7: Output Pin 6 (I2S_DA_OUT)
DPL 4519G
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
N GND Fig. 4-8: Input/Output Pins 2 and 3 (I2C_CL, I2C_DA)
Fig. 4-6: 64-pin PSDIP package
Fig. 4-9: Input Pins 7, 17, 21, 22, 70, and 80 (I2S_DA_IN1..3, RESETQ, TESTEN, STANDBYQ)
DVSUP
23 k
23 k
GND ADR_SEL Fig. 4-10: Input Pin 79 (ADR_SEL)
Micronas
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DPL 4519G
PRELIMINARY DATA SHEET
DVSUP P N GND Fig. 4-11: Input/Output Pins 4, 5, 77, and 78 (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
AHVSUP
0...1.2 mA
3.3 k
Fig. 4-16: Output Pins 24, 25, 27, 28 and 30 (DACA_R/L, DACM_R/L, DACM_SUB)
P
Gain=0.5 500 k
125 k 3.75 V
3-30 pF
Fig. 4-17: Pin 45 (AGNDC) N
2.5 V
3-30 pF
26 pF 120 k
Fig. 4-12: Output/Input Pins 71, 72, and 74 (XTALIN, XTALOUT, AUD_CL_OUT)
300 3.75 V 0...2 V
Fig. 4-18: Output Pins 33, 34, 36, and 37 (SC_2_OUT_R/L, SC_1_OUT_R/L) Fig. 4-13: Capacitor Pins 38 and 40 (CAPL_A, CAPL_M)
24 k 3.75 V
Fig. 4-14: Input Pin 60 (MONO_IN)
40 k 3.75 V
Fig. 4-15: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57 (SC4-1_IN_L/R)
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PRELIMINARY DATA SHEET
DPL 4519G
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Package Power Dissipation PSDIP64 PQFP80 PLQFP64 Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors - SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SCn_OUT_s3) DACp_s3) CAPL_p,3) AGNDC -0.3 -20 -0.3 -5
4), 5) 4)
Pin Name - - AHVSUP DVSUP AVSUP AVSUP, DVSUP
Min. 0 -40 -0.3 -0.3 -0.3 -0.5
Max. 701) 125 9.0 6.0 6.0 0.5
Unit C C V V V V
1300 1000 9601) VSUP2+0.3 +20 VSUP1+0.3 +5
4), 5) 4)
mW
VIdig IIdig VIana IIana IOana IOana ICana
1) 2) 3) 4) 5)
V mA2) V mA2)
4)
4)
PLQFP64: 65 C positive value means current flowing into the circuit "n" means "1", "2", "3", or "4", "s" means "L" or "R", "p" means "M" or "A" The analog outputs are short circuit proof with respect to First Supply Voltage and ground. Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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DPL 4519G
4.6.2. Recommended Operating Conditions (TA = 0 to 70 C) 4.6.2.1. General Recommended Operating Conditions Symbol VSUP1 Parameter First Supply Voltage (8-V Operation) First Supply Voltage (5-V Operation) VSUP2 VSUP3 tSTBYQ1 Second Supply Voltage Third Supply Voltage STANDBYQ Setup Time before Turn-off of Second Supply Voltage DVSUP AVSUP STANDBYQ, DVSUP Pin Name AHVSUP Min. 7.6 4.75 4.75 4.75 1
PRELIMINARY DATA SHEET
Typ. 8.0 5.0 5.0 5.0
Max. 8.7 5.25 5.25 5.25
Unit V V V V s
4.6.2.2. Analog Input and Output Recommendations Symbol CAGNDC Parameter AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA
1)
Pin Name AGNDC
Min. -20% -20%
Typ. 3.3 100 330
Max.
Unit F nF nF
DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor
SCn_IN_s1)
-20%
2.0 MONO_IN SCn_OUT_s1) 10 6.0 CAPL_M, CAPL_A DACM_s, DACA_s1) -10% 10 1 +10% 2.0
VRMS VRMS k nF F nF
"n" means "1", "2", or "3", "s" means "L" or "R", "p" means "M" or "A"
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PRELIMINARY DATA SHEET
DPL 4519G
4.6.2.3. Crystal Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit
General Crystal Recommendations fP RR C0 CL Crystal Parallel Resonance Frequency at 12 pF Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432 8 6.2 25 7.0 MHz pF pF pF
PSDIP approx. 1.5 P(L)QFP approx. 3.3
Crystal Recommendations for Master-Slave Applications (DPL Clock must perform synchronization to I2S clock) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -20 -20 19 18.431 24 18.433 +20 +20 ppm ppm fF MHz
Crystal Recommendations for other Applications (No synchronization to I2S clock possible) fTOL DTEM fCL Accuracy of Adjustment Frequency Variation versus Temperature Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -100 -50 18.429 +100 +50 18.435 ppm ppm MHz
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF) VXCA
1)
External Clock Amplitude
XTAL_IN
0.7
Vpp
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as "start value". To define the capacitor size, reset the DPL without transmitting any further I2C telegrams. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.
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DPL 4519G
4.6.3. Characteristics
PRELIMINARY DATA SHEET
at TA = 0 to 70 C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values at TA = 60 C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature Main (M) = Main Channel, Aux (A) = Aux Channel
4.6.3.1. General Characteristics
Symbol Supply ISUP1A First Supply Current (active) (AHVSUP = 8 V) AHVSUP 18 12 First Supply Current (active) (AHVSUP = 5 V) 12 8 ISUP2A ISUP3A ISUP1S Second Supply Current (active) (DVSUP = 5 V) Third Supply Current (active) First Supply Current (AHVSUP = 8 V) First Supply Current (AHVSUP = 5 V) Clock fCLOCK DCLOCK tJITTER VxtalDC tStartup VACLKAC VACLKDC routHF_ACL Clock Input Frequency Clock High to Low Ratio Clock Jitter (Verification not provided in Production Test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V/s Audio Clock Output AC Voltage Audio Clock Output DC Voltage HF Output Resistance XTAL_IN, XTAL_OUT AUD_CL_OUT 1.2 0.4 140 2.5 0.4 1.8 0.6 2 XTAL_IN 45 18.432 55 50 MHz % ps V ms Vpp VSUP3 load = 40 pF Imax = 0.2 mA DVSUP AVSUP AHVSUP 70 9 5.6 3.7 25 17 17 11 85 13 7.7 5.1 mA mA mA mA mA mA mA mA Standby Mode STANDBYQ = low Volume Main and Aux 0 dB Volume Main and Aux -30 dB Volume Main and Aux 0 dB Volume Main and Aux -30 dB Parameter Pin Name Min. Typ. Max. Unit Test Conditions
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PRELIMINARY DATA SHEET
DPL 4519G
4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Digital Input Levels VDIGIL VDIGIH ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL Digital Input Low Voltage Digital Input High Voltage Input Impedance Digital Input Leakage Current ADR_SEL Input Low Voltage ADR_SEL Input High Voltage Input Current ADR_SEL 0.8 -500 -220 220 Digital Output Levels VDCTROL VDCTROH Digital Output Low Voltage Digital Output High Voltage D_CTR_I/O_0 D_CTR_I/O_1 VSUP2 - 0.3 0.4 V V IDDCTR = 1 mA IDDCTR = -1 mA 500 -1 STANDBYQ D_CTR_I/O_0/1 0.5 5 1 0.2 0.2 VSUP2 VSUP2 pF A VSUP2 VSUP2 A A UADR_SEL= DVSS UADR_SEL= DVSUP 0 V < UINPUT< DVSUP D_CTR_I/O_0/1: tri-state
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DPL 4519G
4.6.3.3. Reset Input and Power-Up
Symbol Parameter Pin Name Min. Typ. Max.
PRELIMINARY DATA SHEET
Unit
Test Conditions
RESETQ Input Levels VRHL VRLH ZRES IRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Impedance Input Pin Leakage Current -1 RESETQ 0.3 0.45 0.4 0.55 5 1 VSUP2 VSUP2 pF A 0 V < UINPUT< DVSUP
DVSUP AVSUP
VSUP2 - 10%
t/ms
RESETQ
0.45xVSUP2 0.3...0.4xVSUP2
Low-to-High Threshold
Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms
High-to-Low Threshold
0.3 x VSUP2 means 1.5 Volt with VSUP2 = 5.0 V t/ms
Reset Delay >2 ms
Internal Reset
High
Low
t/ms Fig. 4-19: Power-up sequence
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PRELIMINARY DATA SHEET
DPL 4519G
4.6.3.4. I2C-Bus Characteristics
Symbol VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 Parameter I2C-BUS Input Low Voltage I2C-BUS Input High Voltage Pin Name I2C_CL, I2C_DA 0.6 120 120 55 55 I2C_CL 500 500 1.0 I2C_CL, I2C_DA 0.4 1.0 15 100 Min. Typ. Max. 0.3 Unit VSUP2 VSUP2 ns ns ns ns ns ns MHz V A ns ns fI2C = 1 MHz II2COL = 3 mA VI2COH = 5 V Test Conditions
I2C START Condition Setup Time I C STOP Condition Setup Time I C-Data Setup Time before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C-Clock Low Pulse Time I2C-Clock High Pulse Time
2 2
I2C-BUS Frequency I2C-Data Output Low Voltage I C-Data Output High Leakage Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock
2
1/FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA as input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA as output
TI2COL1
Fig. 4-20: I2C bus timing diagram
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DPL 4519G
4.6.3.5. I2S-Bus Characteristics
Symbol VI2SIL VI2SIH ZI2SI ILEAKI2S VI2SOL VI2SOH fI2SOWS fI2SOCL RI2S10/I2S20 Parameter Input Low Voltage Input High Voltage Input Impedance Input Leakage Current I S Output Low Voltage I2S Output High Voltage I2S-Word Strobe Output Frequency I2S-Clock Output Frequency I2S-Clock Output High/Low-Ratio
2
PRELIMINARY DATA SHEET
Pin Name I2S_CL I2S_WS I2S_CL3 I2S_WS3 I2S_DA_IN1..3
Min.
Typ.
Max. 0.2
Unit VSUP2 VSUP2
Test Conditions
0.5 5 -1 1 0.4 VSUP2 - 0.3 48.0 1.536 0.9 3.072 1.0 12.288 1.1
pF A V V kHz MHz 0 V < UINPUT< DVSUP II2SOL = 1 mA II2SOH = -1 mA
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL
Synchronous I2S Interface ts_I2S I2S Input Setup Time before Rising Edge of Clock I2S Input Hold Time after Rising Edge of Clock I2S Output Delay Time after Falling Edge of Clock I2S-Word Strobe Input Frequency I2S-Clock Input Frequency I S-Clock Input Ratio
2 2
I2S_DA_IN1/2 I2S_CL
12
ns
for details see Fig. 4-21 "I2S timing diagram (synchronous interface)"
th_I2S td_I2S
40 I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL 1.536 0.9 48.0 3.072 12.288 1.1 28
ns ns CL=30 pF
fI2SWS fI2SCL RI2SCL
kHz MHz
Asynchronous I S Interface ts_I2S3 th_I2S3 fI2S3WS fI2S3CL RI2S3CL I2S3 Input Setup Time before Rising Edge of Clock I2S3 Input Hold Time after Rising Edge of Clock I2S3-Word Strobe Input Frequency I2S3-Clock Input Frequency I2S3-Clock Input Ratio I2S_CL3 I2S_WS3 I2S_DA_IN3 4 40 I2S_WS3 I2S_CL3 0.9 5 50 3.2 1.1 ns ns kHz MHz for details see Fig. 4-22 "I2S timing diagram (asynchronous interface)"
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PRELIMINARY DATA SHEET
DPL 4519G
1/FI2SWS I2S_WS
MODUS[6] = 0 MODUS[6] = 1
Detail C
I2S_CL Detail A I2S_DA_IN*)
R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel Detail B I2S_DA_OUT R LSB
L MSB L LSB R MSB
16/32 bit right channel
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Data: MSB first, I2S synchronous master
1/FI2SWS I2S_WS
MODUS[6] = 0 MODUS[6] = 1
Detail C
I2S_CL Detail A I2S_DA_IN*)
R LSB L MSB L LSB R MSB R LSB L LSB
16,18...32 bit left channel Detail B I2S_DA_OUT R LSB
L MSB
16, 18...32 bit right channel
16, 18...32 bit left channel
L LSB R MSB R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S synchronous slave
Note:
1) I2S_DA_IN can be - I2S_DA_IN1, - I2S_DA_IN2, or - I2S_DA_IN2/3
Detail C
I2S_CL
1/FI2SCL
Detail A,B
I2S_CL
Ts_I2S Ts_I2S I2S_DA_IN1) I2S_WS as INPUT
Th_I2S
Td_I2S
Td_I2S
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4-21: I2S timing diagram (synchronous interface)
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DPL 4519G
PRELIMINARY DATA SHEET
I2S_CL3 1/FI2S3WS
Left sample (I2S_CONFIG[10] = 0) Right sample (I2S_CONFIG[10] = 0) Right sample (I2S_CONFIG[10] = 1) Left aligned (I2S_CONFIG[9] = 0) MSB 16,18...32 Bit data & clocks allowed Left aligned (I2S_CONFIG[9] = 1) 16,18...32 Bit data & clocks allowed MSB
I2S_WS3
Left sample (I S_CONFIG[10] = 1)
2
I2S_DA_IN3
I2S_DA_IN3
MSB
MSB Right aligned (I2S_CONFIG[11] = 1, I2S_CONFIG[9] = 0) 16 Bit data & 16...32 clocks allowed
I2S_DA_IN3
LSB
LSB
1/FI2S3CL I2S_CL3
Ts_I2S3 Th_I2S3
I2S_DA_IN3 Ts_I2S3
I2S_WS3
Fig. 4-22: I2S timing diagram (asynchronous interface)
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Analog Ground VAGNDC0 AGNDC Open Circuit Voltage AHVSUP = 8 V AHVSUP = 5 V RoutAGN AGNDC Output Resistance AHVSUP = 8 V AHVSUP = 5 V Analog Input Resistance RinSC RinMONO
1)
AGNDC 3.8 2.5 V V
Rload 10 M
3 V VAGNDC 4 V 70 47 125 83 180 120 k k
SCART Input Resistance from TA = 0 to 70 C MONO Input Resistance from TA = 0 to 70 C
SCn_IN_s1) MONO_IN
25 15
40 24
58 35
k k
fsignal = 1 kHz, I = 0.05 mA fsignal = 1 kHz, I = 0.1 mA
"n" means "1", "2", "3", or "4";
"s" means "L" or "R"
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PRELIMINARY DATA SHEET
DPL 4519G
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level for Analog-to-Digital-Conversion (AHVSUP=8 V) Analog Input Clipping Level for Analog-to-Digital-Conversion (AHVSUP=5 V) SCART Outputs RoutSC dVOUTSC ASCtoSC frSCtoSC VoutSC SCART Output Resistance Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output Signal Level at SCART-Output (AHVSUP=8 V) Signal Level at SCART-Output (AHVSUP=5 V) Main and Aux Outputs RoutMA Main/Aux Output Resistance DACp_s1) 2.1 2.1 1.80 1.12 1.23 0.76 "p" means "M" or "A" 3.3 4.6 5.0 2.28 1.60 1.51 1.04 k k V mV V mV VRMS VRMS fsignal = 1 kHz, I = 0.1 mA Tj = 27C from TA = 0 to 70C Volume = 0 dB Volume = -30 dB Volume = 0 dB Volume = -30 dB fsignal = 1 kHz full scale Digital Input from I2S Volume = 0 dB SCn_IN_s,1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) SCn_OUT_s1) 200 200 -70 -1.0 -0.5 1.8 1.17 1.9 1.27 330 460 500 +70 +0.5 +0.5 2.0 1.37 mV dB dB VRMS VRMS fsignal = 1 kHz with resp. to 1 kHz 20 Hz to 20 000 Hz fsignal = 1 kHz full scale Digital Input from I2S fsignal = 1 kHz, I = 0.1 mA, Tj = 27C, TA = 0 to 70C SCn_IN_s,1) MONO_IN 2.00 2.25 VRMS fsignal = 1 kHz
1.13
1.51
VRMS
VoutDCMA
DC-Level at Main/Aux-Output (AHVSUP=8 V) DC-Level at Main/Aux-Output (AHVSUP=5 V)
2.04 61 1.36 40 1.37 0.90
VoutMA
Signal Level at Main/Aux-Output (AHVSUP=8 V) Signal Level at Main/Aux-Output (AHVSUP=5 V)
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
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DPL 4519G
4.6.3.7. Power Supply Rejection
Symbol Parameter Pin Name Min. Typ. Max.
PRELIMINARY DATA SHEET
Unit
Test Conditions
PSRR: Rejection of Noise on AHVSUP at 1 kHz PSRR AGNDC From Analog Input to I S Output From Analog Input to SCART Output From I2S Input to SCART Output From
1) 2
AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1) "p" means "M" or "A"
80 70 70
dB dB dB
60 80
dB dB
I2S
Input to Main/Aux Output
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
4.6.3.8. Analog Performance
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Specifications for AHSUP=8 V SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 90 93 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Volume = 0 dB
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
93
96
dB
from I2S Input to SCART Output from I2S Input to Main/Aux-Output THD Total Harmonic Distortion from Analog Input to I2S Output
90 90
93 93
dB dB
MONO_IN, SCn_IN_s1)
0.01
0.03
%
Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) DACA_s, DACM_s1) "p" means "M" or "A"
0.01
0.03
%
from I2S Input to SCART Output from put
1)
0.01 0.01
0.03 0.03
% %
I2S
Input to Main or Aux Out-
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
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PRELIMINARY DATA SHEET
DPL 4519G
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Specifications for AHSUP=5 V SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 87 90 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Volume = 0 dB
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
90
93
dB
from I2S Input to SCART Output from I2S Input to Main/Aux-Output for Analog Volume at 0 dB for Analog Volume at -30 dB THD Total Harmonic Distortion from Analog Input to I2S Output
87 87 75
90 90 80
dB dB dB
MONO_IN, SCn_IN_s1)
0.03
0.1
%
Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) DACA_s, DACM_s1) "p" means "M" or "A"
0.1
%
from I2S Input to SCART Output from I2S Input to Main or Aux Output
1)
0.1 0.1
% %
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
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PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Crosstalk Specifications XTALK Crosstalk Attenuation Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 k unweighted 20 Hz...20 kHz 80 80 80 80 dB dB dB dB unweighted 20 Hz...20 kHz 75
1)
between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SCn_OUT1) SC1_IN or SC2_IN I S Output
2
SC3_IN I2S Output I2S Input SCn_OUT1)
between left and right channel within Main or Aux Output pair I2S Input DACp1) between SCART Input/Output pairs D = disturbing program O = observed program D: MONO/SCn_IN SCn_OUT O: MONO/SCn_IN SCn_OUT1) D: MONO/SCn_IN SCn_OUT or unsel. O: MONO/SCn_IN I2S Output D: MONO/SCn_IN SCn_OUT O: I2S Input SCn_OUT1) D: MONO/SCn_IN unselected O: I2S Input SC1_OUT1) Crosstalk between Main and Aux Output pairs I2S Input DSP DACp1) 100 95 100 100 dB dB dB dB dB
(unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel
90
dB
(unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel (unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel
XTALK
Crosstalk from Main or Aux Output to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP SCn_OUT O: I2S Input DACp1) D: MONO/SCn_IN/DSP SCn_OUT O: I2S Input DACp1) D: I2S Input DACp O: MONO/SCn_IN SCn_OUT1) D: I2S Input DACM O: I2S Input SCn_OUT1) 80 85 95 95 "p" means "M" or "A" dB dB dB dB
SCART output load resistance 10 k SCART output load resistance 30 k
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
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PRELIMINARY DATA SHEET
DPL 4519G
5. Appendix A: Application Information 5.1. Phase Relationship of Analog Outputs The analog output signals: Main, Aux, and SCART2 all have the same phases. The SCART1 output has opposite phase. Using the I2S-outputs for other DSPs or D/A converters, care must be taken to adjust for the correct phase.
I2S_IN1/2/3
I2S_OUT1/2
Main Aux
SCART1-Ch. Audio Baseband Processing SCART1 SCART2 SCART3 SCART4 MONO MONO, SCART1...4 SCART Output Select SCART2 SCART1
Fig. 5-1: Phase diagram of the DPL 4519G
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DPL 4519G
5.2. Application Circuit
C s. section 4.6.2.
PRELIMINARY DATA SHEET
8 V(5 V)
3.3 F + 100 nF 18.432 MHz + 10 F + 10 F
XTAL_IN (62) 71
AGNDC (42) 45
XTAL_OUT (63) 72
CAPL_M (40) 40
CAPL_A (38) 38
1 F
DACM_L (29) 28 1 nF DACM_R (28) 27
left
1 F
330 nF
60 (55) MONO_IN
right
1 nF
330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF
56 (52) SC1_IN_L 57 (53) SC1_IN_R 55 (51) ASG 53 (49) SC2_IN_L 54 (50) SC2_IN_R 52 (48) ASG 50 (46) SC3_IN_L 51 (47) SC3_IN_R 49 (45) ASG 47 (43) SC4_IN_L 48 (44) SC4_IN_R DACA_R (25) 24 DACA_L (26) 25 DACM_SUB (31) 30
1 F
Subwoofer
1 nF
1 F
Center
1 nF
1 F
Surround
1 nF
5V 5V
DVSS
330 nF
DPL 4519G
SC1_OUT_L (37) 37
80 (7) STANDBYQ 79 (6) ADR_SEL
100 22 F
+
SC1_OUT_R (36) 36
100 22 F
+
DVSS 3 (10) I2C_DA 2 (9) I2C_CL SC2_OUT_L (34) 34
100 22 F
+
SC2_OUT_R (33) 33 D_CTR_I/O_0 (5) 78 5 (12) I2S_WS 4 (11) I2S_CL 7 (14) I2S_DA_IN1 17 (20) I2S_DA_IN2 6 (13) I2S_DA_OUT 39 (39) AHVSUP 21 (24) RESETQ 13 (18) DVSUP 66 (57) AVSUP 16 (19) DVSS 62 (56) AVSS TESTEN (61) 70 43 (41) AHVSS 35 (35) VREF1 26 (27) VREF2 AUD_CL_OUT (1) 74 D_CTR_I/O_1 (4) 77
100 22 F
+
AHVSS
RESETQ (from Controller, see section 4.6.3.3.)
220 pF 470 pF 1.5 nF 10 F
470 pF 1.5 nF 10 F
470 pF 1.5 nF 10 F
Note:
Decoupling capacitors from - DVSUP to DVSS, - AVSUP to AVSS, and - AHVSUP to AHVSS are recommended as closely as possible to supply pins (see application note on page 42).
AHVSS
AHVSS
5V
5V
8V (5 V)
Note: Pin numbers refer to the PQFP80 package, numbers in brackets refer to the PSDIP64 package.
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AHVSS
AVSS
Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Micronas
63
DPL 4519G
6. Data Sheet History 1. Preliminary data sheet: "DPL 4519G Sound Processor for Digital and Analog Surround Systems", Oct. 31, 2000, 6251-512-1PD. First release of the preliminary data sheet.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-512-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
64
Micronas

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